Advanced Computer Architecture - Assignment - Tran Ngoc Thinh
| Exercise1 |
| 1 Design an L1 cache (number of bits for tag, entry, …) for a CPU with 32-bit address in 3 following types. The cache size is 32KB, block (line) size is 32 byte • Direct mapped • Fully Associative • 4 way associative |
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28/12/2022
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- 4/25/2013 dce 2011 Exercise 3 How much faster/slower is a unified 32KB cache than a separated 16KB I/16KB D cache if the miss rate is ones in the following slide table, and there are 70% instructions are LD/ST. Assumed that unified cache has 1-port only. The hit time is 1 cycle and miss penalty is 50 cycles 3 dce 2011 Separated cache or unified cache? Size I-Cache D-Cache U-Cache 8KB 8.16 44.0 63.0 16KB 3.82 40.9 51.0 32KB 1.36 38.4 43.3 64KB 0.61 36.9 39.4 128KB 0.30 35.3 36.2 256KB 0.02 32.6 32.9 Misses per 1000 instructions 4 2
