Advanced Computer Architecture - Review of Instructions Set Architecture - Tran Ngoc Thinh

Nội dung text: Advanced Computer Architecture - Review of Instructions Set Architecture - Tran Ngoc Thinh

1. 2/25/2013 dce 2011 Outline  Instruction structure  ISA styles  Addressing modes  Analysis on instruction set  Case study: MIPS Computer Architecture, Chapter 2 3 dce 2011 Machine Instruction Computer can only understand binary values The operation of a computer is defined by predefined binary values called Instruction Computer Architecture, Chapter 2 4 2
2. 2/25/2013 dce 2011 ISA Styles Input1 Input2 ISA Styles? Operation • Stack • Accumulator Output • Register memory/ Memory memory • Register register/load store 7 dce 2011 ISA Styles: Stack TOS Stack Element C= A+B? Stack Element PUSH A PUSH B ADD POP C  Stack: The operands is on top of stack. The result is push back to the stack  (+): Code density, simple hardware  (-): Low parallelism, stack bottle-neck Computer Architecture, Chapter 2 8 4
3. 2/25/2013 dce 2011 ISA Styles: Register-Memory Register Input, Output: Register Register or Memory Register C= A+B? Memory LOAD R1, A ADD R3, R1, B STORE R3, C Computer Architecture, Chapter 2 ©2011, Dr. Dinh Duc Anh Vu 11 dce 2011 ISA Styles: Register-Register Register C= A+B? Register Register LOAD R1, A LOAD R2, B ADD R3, R1, R2 STORE R3, C  Register-Register: All operation is on registers  Need specific Load and Store instruction to access memory Computer Architecture, Chapter 2 12 6
4. 2/25/2013 dce 2011 Evolution of Instruction Sets Single Accumulator (EDSAC 1950) Accumulator + Index Registers (Manchester Mark I, IBM 700 series 1953) Separation of Programming Model from Implementation High-level Language Based Concept of a Family (B5000 1963) (IBM 360 1964) General Purpose Register Machines Complex Instruction Sets Load/Store Architecture (CDC 6600, Cray 1 1963-76) (Vax, Intel 432 1977-80) RISC (Mips,Sparc,HP-PA,IBM RS6000,PowerPC . . .1987) LIW/”EPIC”? (IA-64. . .1999) Computer Architecture, Chapter 2 15 dce 2011 Instruction set design  The design of an Instruction Set is critical to the operation of a computer system.  Including many aspects • Operation repertoire • Addressing modes • Data types • Instruction format • Registers Computer Architecture, Chapter 2 16 8
5. 2/25/2013 dce 2011 Operations There must certainly be instructions for performing the fundamental arithmetic operations Burkes, Goldstine and Von Neumann, 1947 How many programs have “IF” statement? -> Branch instructions How many programs have “Call” statement? -> Call, Return instructions How many programs have to access memory? and so on Computer Architecture, Chapter 2 19 dce 2011 Operations Operator type Example Arithmetic & Logical Integer arithmetic and logical operations: add, and, subtract Data transfer Loads-stores (move instructions on machines with memory addressing) Control Branch, jump, procedure call and return, trap System Operating system call, Virtual memory management instructions Floating point Floating point instructions: add, multiply Decimal Decimal add, decimal multiply, decimal to character conversion String String move, string compare, string search Graphic Pixel operations, compression/decompression operations Computer Architecture, Chapter 2 20 10
6. 2/25/2013 dce 2011 Operations  Jump: unconditional (Goto statement)  Branch: conditional (if/else statement)  Call/return: procedure call/return Computer Architecture, Chapter 2 23 dce 2011 Operations  PC-Relative addressing: short and position- indipendent jump  Register indirect addressing: Long jump, dynamic library, virtual function, Computer Architecture, Chapter 2 24 12
7. 2/25/2013 dce 2011 Addressing Modes The way the processor refers to the operands is called addressing mode The addressing modes can be classified based on: • The source of data: Immediate, registers, memory • The address calculation: Direct, indirect, indexed Computer Architecture, Chapter 2 27 dce 2011 Addressing modes - Immediate addressing: the operand is put in the instruction Ex: ADD R0, #10 - Register addressing: the index of the register which contains the operand is specified in the instruction Ex: ADD R0, R1 - Direct addressing: the address of the operand is put in the instruction Ex: ADD R0, (100) Computer Architecture, Chapter 2 28 14
8. 2/25/2013 dce 2011 Addressing mode Computer Architecture, Chapter 2 31 dce 2011 Addressing mode Computer Architecture, Chapter 2 32 16
9. 2/25/2013 dce 2011 Operand types  Character: - ACSII (8-bit): amost always used - Unicode (16-bit): sometime  Integer: 2’s complement - Short: 16 bit - Long: 32 bit  Floating point: - Single precision: 32 bit - Double precision: 64 bit Computer Architecture, Chapter 2 35 dce 2011 Operand types  Business - Binary Coded Decimal (BCD): Accurately represents decimal fraction  DSP - Fixed point - Block floating point  Graphic: RGBA or XYZW - 8-bit, 16-bit or single precision floating point Computer Architecture, Chapter 2 36 18
10. 2/25/2013 dce 2011 Instruction format  Instruction must be encoded to binary values  Effect the size of compiled program  Easy to decode -> Simple to implement  Support as many registers and addressing modes as possible MIPS Opcode Rs Rt Rd Shamt Funct Ex: ADD $t0, $s1, $s2 000000 10001 10010 01000 00000 100000 0x02324020 Computer Architecture, Chapter 2 39 dce 2011 Instruction format Addr Addr Addr Addr Opcode Specifier Field Specifier Field Variable insrtuction length (e.g. VAX, X86) Addr Addr Addr Opcode Field 1 Field 2 Field 3 Fixed insrtuction length (e.g. ARM, MIPS, PowerPC) Hybrid: to gain high code density, use 2 type of fixed length instruction (e.g. MIPS16, Thumb) Computer Architecture, Chapter 2 40 20
11. 2/25/2013 dce 2011 The MIPS ISA • Instruction Categories Registers – Load/Store R0 - R31 – Computational – Jump and Branch – Floating Point • coprocessor PC – Memory Management HI LO – Special • 3 Instruction Formats: all 32 bits wide OP rs rt rd shamt funct R-format OP rs rt immediate I-format OP jump target J-format Computer Architecture, Chapter 2 43 dce 2011 MIPS (RISC) Design Principles • Simplicity favors regularity – fixed size instructions – small number of instruction formats – opcode always the first 6 bits • Smaller is faster – limited instruction set – limited number of registers in register file – limited number of addressing modes • Make the common case fast – arithmetic operands from the register file (load-store machine) – allow instructions to contain immediate operands • Good design demands good compromises – Same instruction length – Single instruction format => 3 instruction formats Computer Architecture, Chapter 2 44 22
12. 2/25/2013 dce 2011 MIPS - Endianness • Big Endian: Most-significant byte at lowest address of a word • Little Endian: Least-significant byte at lowest address of a word • MIPS is Big-endian dce 2011 MIPS R-Format instructions Op Rs Rt Rd Shamt Funct • Op: opcode • Rs: First source register number • Rt: Second source register number • Rd: Destination register number • Shamt: shift amount – Number of bit-shift –(left/right) • Funct: Extend opcode – ALU function to encode the data path operation Execution: Rd <- Rs func Rt Computer Architecture, Chapter 2 48 24
13. 2/25/2013 dce 2011 Logical operations • AND, OR, XOR, XNOR (bit-wise) • Ex: OR $t0, $t1, $t2 #$t0 = $t1 | $t2 • Please calculate the encoded instruction word for the above instruction • Shift left, shift right • Shamt indicates the number of bit to shift • Ex: SLL $t2, $s0, 8 000000 00000 10000 01010 01000 000000 Computer Architecture, Chapter 2 51 dce 2011 Logical operations • Shift Right Arithmetic (SRA) use MSB as the shift-in bit • Ex: SRA $t2, $s0, 8 000000 00000 10000 01010 01000 000011 • Why is there no SLA? • Why is there no NOT? Computer Architecture, Chapter 2 52 26
14. 2/25/2013 dce 2011 Immidiate arithmetic and logical Opcode Rs Rt 16-bit Immediate Value • Arithmetic and Logical instruction with immediate value - Op: opcode - Rs: source register - Rt: destination register - Constant: immediate value (-32768 to 32767) dce 2011 Immediate arithmetic and logical • Ex: ADDI $t0, $t1, 0x0005 001000 01001 01000 0000000000000101 • Ex: ORI $t0, $t1, 0xFF00 001101 01001 01000 1111111100000000 • Why is there no SUBI? Computer Architecture, Chapter 2 56 28
15. 2/25/2013 dce 2011 PC-Relative Opcode Rs Rt 16-bit Immediate Value • Near branch instructions – Rs: source register number – Rt: source register number – Target address = PC + offset x 4 – PC already incremented by 4 by this time • EX: BEQ $s0, $s1, 256 – if($s0 == $s1) goto PC+256; 000100 10000 10001 0000000100000000 Computer Architecture, Chapter 2 59 dce 2011 MIPS J-format Instructions Opcode 26-bit Offset • Jump (J and JAL) • Pseudo-Direct addressing – Cannot put 32-bit value in instruction – Target address = PC31 28: (26-bit offset ×4) • Ex: J 0x01000000 000010 00000001000000000000000000000000 30
16. 2/25/2013 dce 2011 Atomic operation • Example atomic swap: try: ADD $t0, $zero, $s4 //$t0 = $s4 LL $t1, 0($s1) //$t1 = mem($s1) SC $t0, 0($s1) //mem($s1) = $t0 BEQ $t0, $zero, try //if mem($s1) changed, //try again //else mem($s1) = $t0 ADD $s4, $zero, $t1//$s4 = $t1 Computer Architecture, Chapter 2 63 dce 2011 Constant (Immediate) value • Small constants are used quite frequently (50% of operands in many common programs) Ex: $t0 = 0x1234 ADDI $t0, $zero, 0x1234 • How to use 32-bit constant? Ex: $t0 = 0x12345678 LUI $t0, 0x1234 ORI $t0, $t0, 0x5678 Computer Architecture, Chapter 2 64 32
17. 2/25/2013 dce 2011 Reference [1]Mips instruction set reference.pdf Computer Architecture, Chapter 2 67 34