Computer Operating System - Chapter 9: Main Memory

Background
! Contiguous Memory Allocation
! Paging
! Structure of the Page Table
! Swapping
! Example: The Intel 32 and 64-bit Architectures
! Example: ARMv8 Architecture

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Chapter 9: Outline ! Background ! Contiguous Memory Allocation ! Paging ! Structure of the Page Table ! Swapping ! Example: The Intel 32 and 64-bit Architectures ! Example: ARMv8 Architecture Operating System Concepts 2 Silberschatz, Galvin and Gagne ©2018
Background ! Program must be brought (from disk) into memory and placed within a process for it to be run ! Main memory and registers are only storage CPU can access directly " Register access is done in one CPU clock (or less) " Main memory access can take many cycles, causing a stall ! Cache sits between main memory and CPU registers ! Memory Management Unit (MMU) only sees a stream of: " addresses and read requests, " Or, address + data and write requests ! Protection of memory required to ensure correct operation Operating System Concepts 4 Silberschatz, Galvin and Gagne ©2018
Hardware Address Protection ! CPU must check every memory access generated in user mode to be sure it is between (base) and (base + limit) for that user ! Instructions to loading the base and limit registers are privileged Operating System Concepts 6 Silberschatz, Galvin and Gagne ©2018
Binding of Instructions and Data to Memory ! Address binding of instructions and data to memory addresses can happen at three different stages " Compile time: If memory location known a priori (e.g., Arduino), absolute code can be generated; must recompile code if starting location changes " Load time: Must generate relocatable code if memory location is not known at compile time " Execution time: Binding delayed until run time if the process can be moved from one memory segment to another during its execution 4 Need hardware support for address maps (e.g., base and limit registers) Operating System Concepts 8 Silberschatz, Galvin and Gagne ©2018
Logical vs. Physical Address Space ! The concept of a logical address space that is bound to a separate physical address space is central to proper memory management " Logical address – generated by the CPU; also referred to as virtual address " Physical address – address seen by the Memory Management Unit ! Logical and physical addresses are the same in compile-time and load-time address-binding schemes; logical (virtual) and physical addresses differ in execution-time address-binding scheme " Logical address space is the set of all logical addresses generated by a program " Physical address space is the set of all physical addresses generated by a program Operating System Concepts 10 Silberschatz, Galvin and Gagne ©2018
Memory-Management Unit (Cont.) ! E.g., Consider a simple scheme which is a generalization of the base-register scheme " The base register now called relocation register " The value in the relocation register is added to every address generated by a user process at the time it is sent to memory ! The user program deals with logical addresses; it never sees the real physical addresses ! Execution-time binding (i.e., logical addresses bound to physical addresses) occurs when reference is made to location in memory Operating System Concepts 12 Silberschatz, Galvin and Gagne ©2018
Dynamic Loading (Cont.) ! Static loading – system libraries and program code combined by the loader into the binary program image ! Dynamic loading – load postponed until execution time ! Small piece of code, stub, used to locate the appropriate memory- resident library routine " Stub replaces itself with the address of the routine, and executes the routine ! Operating system checks if routine is in the memory address space of the process " If not in address space, add to address space ! Dynamic loading is particularly useful for libraries " System also known as shared libraries " Consider applicability to patching system libraries 4 Versioning may be needed Operating System Concepts 14 Silberschatz, Galvin and Gagne ©2018
Dynamic Memory-Allocation Problem ! How to satisfy a memory request of size n from a list of free holes? " First-fit: Allocate the first hole that is big enough " Best-fit: Allocate the smallest hole that is big enough 4 It must search entire list, unless ordered by size 4 Produces the smallest leftover hole " Worst-fit: Allocate the largest hole 4 It must also search entire list 4 Produces the largest leftover hole ! First-fit and best-fit strategies are better than worst-fit in terms of speed and memory utilization Operating System Concepts 18 Silberschatz, Galvin and Gagne ©2018
Fragmentation (Cont.) ! Reduce external fragmentation by compaction " Shuffle memory contents to place all free memory together in one large block " Compaction is possible only if relocation is dynamic, and is done at execution time " I/O problem 4 Latch job in memory while it is involved in I/O 4 Do I/O only into OS buffers ! Now consider that backing store has same fragmentation problems Operating System Concepts 20 Silberschatz, Galvin and Gagne ©2018
Address Translation Scheme ! Address generated by CPU is divided into: " Page number (p) – used as an index into a page table which contains base address of each page in physical memory " Page offset (d) – combined with base address to define the physical memory address that is sent to the Memory Management Unit ! For given logical address space 2m and page size 2n " Number of pages: p = 2m/2n " Offset inside a page: d ⍷ [0,n] page number page offset p d m -n n Operating System Concepts 22 Silberschatz, Galvin and Gagne ©2018
Paging Model of Logical and Physical Memory Page # Frame # Operating System Concepts 24 Silberschatz, Galvin and Gagne ©2018
Paging – Calculating internal fragmentation ! Page size = 2,048 bytes ! Process size (space) = 72,766 bytes " 35 pages + 1,086 bytes ! Internal fragmentation of last page = 2,048 - 1,086 = 962 bytes " Worst case fragmentation = 1 frame – 1 byte " On average fragmentation = 1 / 2 frame size ! So small frame sizes desirable? " But each page table entry takes memory to track ! Page sizes growing over time " Solaris supports two page sizes – 8 KB and 4 MB Operating System Concepts 26 Silberschatz, Galvin and Gagne ©2018
Implementation of Page Table ! Page table is kept in main memory " Page-table base register (PTBR) points to the page table " Page-table length register (PTLR) indicates size of the page table ! In this scheme every data/instruction access requires two memory accesses " One for the page table " one for the data / instruction ! The two-memory-access problem can be solved by the use of a special fast-lookup hardware cache called Translation Look-aside Buffers (TLBs) (also called associative memory) Operating System Concepts 28 Silberschatz, Galvin and Gagne ©2018
Hardware ! Associative memory – parallel search Page # Frame # ! Address translation (p, d) " If p is in associative register, get frame # out " Otherwise get frame # from page table in memory Operating System Concepts 30 Silberschatz, Galvin and Gagne ©2018
Effective Access Time ! Hit ratio – percentage of times that a page number is found in TLB " E.g., An 80% hit ratio means that we find the desired page number in the TLB 80% of the time. ! Suppose that 10 nanoseconds (ns) to access memory. " If we find desired page in TLB then mapped-memory access take 10 ns " Otherwise we need two memory access, so it is 20 ns ! Effective Access Time (EAT) " EAT = 0.80 x 10 + 0.20 x 20 = 12 ns => implying 20% slowdown in access time " Consider a more realistic hit ratio of 99%, EAT = 0.99 x 10 + 0.01 x 20 = 10.1 ns => implying only 1% slowdown in access time Operating System Concepts 32 Silberschatz, Galvin and Gagne ©2018
Hierarchical Page Tables ! Break up the logical address space into multiple page tables ! A simple technique is a two-level page table ! We then page the page table Operating System Concepts 38 Silberschatz, Galvin and Gagne ©2018
Oracle SPARC Solaris (Cont.) ! TLB holds translation table entries (TTEs) for fast hardware lookups " A cache of TTEs reside in a translation storage buffer (TSB) 4 Includes an entry per recently accessed page ! Virtual address reference causes TLB search " If miss, hardware walks the in-memory TSB looking for the TTE corresponding to the address 4 If match found, the CPU copies the TSB entry into the TLB and translation completes 4 If no match found, kernel interrupted to search the hash table – The kernel then creates a TTE from the appropriate hash table and stores it in the TSB, Interrupt handler returns control to the MMU, which completes the address translation. Operating System Concepts 48 Silberschatz, Galvin and Gagne ©2018
Swapping (Cont.) ! Does the swapped out process need to swap back in to same physical addresses? ! Depends on address binding method " Plus consider pending I/O to / from process memory space ! Modified versions of swapping are found on many systems (i.e., UNIX, Linux, and Windows) " Swapping normally disabled " Started if more than threshold amount of memory allocated " Disabled again once memory demand reduced below threshold Operating System Concepts 50 Silberschatz, Galvin and Gagne ©2018
Context Switch Time including Swapping ! If next processes to be put on CPU is not in memory, need to swap out a process and swap in target process ! Context switch time can then be very high ! 100MB process swapping to hard disk with transfer rate of 50MB/sec " Swap out time of 2000ms " Plus swap in of same sized process " Total context switch swapping component time of 4000ms (4 seconds) ! Can reduce if reduce size of memory swapped – by knowing how much memory really being used " System calls to inform OS of memory use via request_memory() and release_memory() Operating System Concepts 52 Silberschatz, Galvin and Gagne ©2018
Swapping on Mobile Systems ! Not typically supported " Flash memory based 4 Small amount of space 4 Limited number of write cycles 4 Poor throughput between flash memory and CPU on mobile platform ! Instead use other methods to free memory if low " iOS asks apps to voluntarily relinquish allocated memory 4 Read-only data thrown out and reloaded from flash if needed 4 Failure to free can result in termination " Android terminates apps if low free memory, but first writes application state to flash for fast restart " Both OSes support paging as discussed below Operating System Concepts 54 Silberschatz, Galvin and Gagne ©2018
Example: The Intel 32 and 64-bit Architectures ! Dominant industry chips ! Pentium CPUs are 32-bit and called IA-32 architecture ! Current Intel CPUs are 64-bit and called IA-64 architecture ! Many variations in the chips, cover the main ideas here Operating System Concepts 56 Silberschatz, Galvin and Gagne ©2018
Example: The Intel IA-32 Architecture (Cont.) ! CPU generates logical address " Selector given to segmentation unit 4 Which produces linear addresses " Linear address given to paging unit 4 Which generates physical address in main memory 4 Paging units form equivalent of MMU 4 Pages sizes can be 4 KB or 4 MB Operating System Concepts 58 Silberschatz, Galvin and Gagne ©2018
Intel IA-32 Page Address Extensions ! 32-bit address limits led Intel to create page address extension (PAE), allowing 32-bit apps access to more than 4GB of memory space " Paging went to a 3-level scheme " Top two bits refer to a page directory pointer table " Page-directory and page-table entries moved to 64-bits in size " Net effect is increasing address space to 36 bits – 64GB of physical page directory page table offset 31 30 29 21 20 12 11 0 4-KB page CR3 register page directory page page pointer table directory table Operating System Concepts 62 Silberschatz, Galvin and Gagne ©2018
Example: ARM Architecture ! Dominant mobile platform chip (Apple iOS and Google Android devices for example) 32 bits ! Modern, energy efficient, 32-bit CPU outer page inner page offset ! 4 KB and 16 KB pages ! 1 MB and 16 MB pages (termed 4-KB sections) or 16-KB ! One-level paging for sections, two-level page for smaller pages ! Two levels of TLBs 1-MB or " Outer level has two micro TLBs 16-MB section (one data, one instruction) " Inner is single main TLB " First inner is checked, on miss outers are checked, and on miss page table walk performed by CPU Operating System Concepts 64 Silberschatz, Galvin and Gagne ©2018
Summary (Cont.) ! One approach to allocating memory is to allocate partitions of contiguous memory of varying sizes. These partitions may be allocated based on three possible strategies: (1) first fit, (2) best fit, and (3) worst fit. ! Modern operating systems use paging to manage memory. In this process, physical memory is divided into fixed-sized blocks called frames and logical memory into blocks of the same size called pages ! When paging is used, a logical address is divided into two parts: a page number and a page offset. The page number serves as an index into a per-process page table that contains the frame in physical memory that holds the page. The offset is the specific location in the frame being referenced. Operating System Concepts 66 Silberschatz, Galvin and Gagne ©2018
Summary (Cont.) ! Swapping allows the system to move pages belonging to a process to disk to increase the degree of multiprogramming. ! The Intel 32-bit architecture has two levels of page tables and supports either 4-KB or 4-MB page sizes. This architecture also supports page- address extension, which allows 32-bit processors to access a physical address space larger than 4 GB. The x86-64 and ARMv9 architectures are 64-bit architectures that use hierarchical paging. Operating System Concepts 68 Silberschatz, Galvin and Gagne ©2018