Computer Operating System - Lecture 9: Memory management - Nguyen Thanh Son

Nội dung text: Computer Operating System - Lecture 9: Memory management - Nguyen Thanh Son

1. Chapter’s Content  Background  Swapping  Contiguous Allocation  Paging  Segmentation  Segmentation with Paging BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 2
2. Binding of Instructions and Data to Memory Address binding of instructions and data to memory addresses can happen at three different stages.  Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes.  Load time: Must generate relocatable code if memory location is not known at compile time.  Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers). BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 4
3. Logical vs. Physical Address Space  The concept of a logical address space that is bound to a separate physical address space is central to proper memory management:  Logical address – generated by the CPU; also referred to as virtual address.  Physical address – address seen by the memory unit.  Logical and physical addresses are the same in compile-time and load-time address-binding schemes; logical (virtual) and physical addresses differ in execution-time address-binding scheme. BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 6
4. Dynamic relocation using a relocation register BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 8
5. Dynamic Linking  Linking postponed until execution time.  Small piece of code, stub, used to locate the appropriate memory-resident library routine.  Stub replaces itself with the address of the routine, and executes the routine.  Operating system needed to check if routine is in processes’ memory address.  Dynamic linking is particularly useful for libraries. BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 10
6. Overlays for a Two-Pass Assembler BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 12
7. Schematic View of Swapping BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 14
8. Hardware Support for Relocation and Limit Registers BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 16
9. Dynamic Storage-Allocation Problem  How to satisfy a request of size n from a list of free holes.  First-fit: Allocate the first hole that is big enough.  Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size. Produces the smallest leftover hole.  Worst-fit: Allocate the largest hole; must also search entire list. Produces the largest leftover hole.  First-fit and best-fit better than worst-fit in terms of speed and storage utilization by simulations.  However, in reality not better in term of storage utilization.  First-fit is generally faster than others. BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 18
10. Paging  Scheme that permits the physical address space of a process to be noncontiguous.  Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8192 bytes).  Divide logical memory into blocks of same size called pages. Size of a frame and of a page is the same.  Keep track of all free frames.  To run a program of size n pages, need to find n free frames and load program.  Set up a page table to translate logical to physical addresses. BK  Internal fragmentation. TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 20
11. Address Translation Architecture BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 22
12. Paging Example BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 24
13. Free Frames Before allocation After allocation BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 26
14. Associative Memory  Associative memory – parallel search Page # Frame # Address translation (A´, A´´)  If A´ is in associative register, get frame # out.  Otherwise get frame # from page table in memory BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 28
15. Address Subdivision BK TP.HCM 07-Feb-17 Faculty of Computer Science & Engineering 30
16. Memory Protection  Memory protection implemented by associating protection bit with each frame.  Valid-invalid bit attached to each entry in the page table:  ―valid‖ indicates that the associated page is in the process’ logical address space, and is thus a legal page.  ―invalid‖ indicates that the page is not in BK the process’ logical address space. TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 32
17. Page Table Structure  Hierarchical Paging  Hashed Page Tables  Inverted Page Tables BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 34
18. Two-Level Paging Example  A logical address (on 32-bit machine with 4K page size) is divided into:  a page number consisting of 20 bits.  a page offset consisting of 12 bits.  Since the page table is paged, the page number is further divided into:  a 10-bit page number.  a 10-bit page offset.  Thus, a logical address is as follows: page number page offset pi p2 d 10 10 12 where pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table. BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 36
19. Address-Translation Scheme  Address-translation scheme for a two- level 32-bit paging architecture BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 38
20. Hashed Page Table BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 40
21. Inverted Page Table Architecture BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 42
22. Shared Pages Example BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 44
23. User’s View of a Program BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 46
24. Segmentation Architecture  Logical address consists of a two tuple: ,  Segment table – maps two-dimensional physical addresses; each table entry has:  base – contains the starting physical address where the segments reside in memory.  limit – specifies the length of the segment.  Segment-table base register (STBR) points to the segment table’s location in memory.  Segment-table length register (STLR) indicates number of segments used by a program; BK segment number s is legal if s < STLR. TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 48
25. Segmentation Architecture (Cont.)  Protection. With each entry in segment table associate:  validation bit = 0 illegal segment  read/write/execute privileges  Protection bits associated with segments; code sharing occurs at segment level.  Since segments vary in length, memory allocation is a dynamic storage-allocation problem.  A segmentation example is shown in the BK TP.HCM following diagram 12-Sep-16 Faculty of Computer Science & Engineering 50
26. Example of Segmentation BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 52
27. Segmentation with Paging – MULTICS  The MULTICS system solved problems of external fragmentation and lengthy search times by paging the segments.  Solution differs from pure segmentation in that the segment-table entry contains not the base address of the segment, but rather the base address of a page table for this segment. BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 54
28. Segmentation with Paging – Intel 386  As shown in the following diagram, the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme. BK TP.HCM 12-Sep-16 Faculty of Computer Science & Engineering 56